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synthesised broadband converter with programmable power 1 SL2101 datasheet noise i 2 c bus controlled pll frequency synthesiser. it is intended primarily for application in double conversion tuners as both the up and down converter and is compatible with hiif frequencies up to 1.4 ghz and all standard tuner if output frequencies. it also contains a programmable power facility for application in systems where power consumption is important. the device contains all elements necessary, with the exception of local oscillator tuning network, loop ?ter and crystal reference to fabricate a complete synthesised block converter, compatible with digital and analogue requirements. ds5526 issue 1.5 january 2002 ordering information SL2101c/kg/np1s (sticks) SL2101c/kg/np1t (tape and reel) features single chip synthesised broadband solution compatible with both up converter and downconverter requirements in double conversion tuner applications incorporates 8 programmable mixer power settings fully downwards compatible with the sl2100 compatible with digital and analogue system requirements (in maximum power setting) cso -65 dbc, ctb -68 dbc (typical, in maximum power setting) extremely low phase noise balanced local oscillator, with i 2 c bus controlled band switching and with very low fundamental and harmonic radiation integral fast mode compliant i 2 c bus controlled pll frequency synthesiser designed for high comparison frequencies and low phase noise performance buffered crystal output for pipelining system reference frequency full esd protection. (normal esd handling procedures should be observed) applications cable telephony double conversion tuners digital terrestrial tuners cable modems data transmit systems data communications systems ?atv description the SL2101 is a fully integrated single chip broadband mixer oscillator with on-board low phase figure 1 - pin allocation xtal cap 28 SL2101 np 28 xtal sda scl bufref vccd vee rf rfb vee vccrf vee ifoutputb vee ifoutput vee vcclo lo lob vcclo vee add vee port p0 drive pump vee vcclo
SL2101 datasheet 2 quick reference data all data applies at maximum power setting with the following conditions unless otherwise stated; a) nominal loads as follows; 1220 mhz output load as in gure (3) 44 mhz output load as in gure (4) b) input signal per carrier of 63 db v * dbm assumes a 75 ? characteristic impedance, and 0 dbm = 109 db v characteristic units rf input operating range 50-1400 mhz input noise gure, ssb 50-860 mhz 6.5-8.5 db 860-1400 8.5-12 db conversion gain 12 db ctb (fully loaded matrix) -68 dbc cso (fully loaded matrix) -65 dbc p1db input referred 110 db v local oscillator phase noise as upconverter ssb @ 10 khz offset -90 dbc/hz ssb @ 100 khz offset -112 dbc/hz local oscillator phase noise as downconverter ssb @ 10 khz offset -93 dbc/hz ssb @ 100 khz offset -115 dbc/hz local oscillator phase noise oor -136 dbc/hz pll spurs on converted output with input @ 60 db v < -70 dbc pll maximum comparison frequency 4 mhz pll phase noise at phase detector -152 dbc/hz
datasheet SL2101 3 functional description the SL2101 is a broadband wide dynamic range mixer oscillator with on-board i 2 c bus controlled pll frequency synthesiser, optimised for application in double conversion tuner systems as both the up and down converter. it also has application in any system where a wide dynamic range broadband synthesised frequency converter is required. the SL2101 is a single chip solution containing all necessary active circuitry and simply requires an external tuneable resonant network for the local oscillator sustaining network. the pin assignment is contained in gure (1) and the block diagram in gure (2). the device also contains a programmable facility to adjust the power in the lna/mixer so allowing power to be traded against intermodulation performance for power critical applications, such as telephony modems. converter section in normal application the rf input is interfaced through appropriate impedance matching and an agc front end to the device input. the rf input preampli er of the device is designed for low noise gure, within the operating region of 50 to 1400 mhz and for high intermodulation distortion intercept so offering good signal to noise plus composite distortion spurious performance when loaded with a multi carrier system. the preampli er also provides gain to the mixer section and back isolation from the local oscillator section. the lna/mixer current and hence signal handling and device power consumption are programmable through the i 2 c bus as tabulated in gure (6). the typical rf input impedance and matching network for broadband upconversion are contained in gures (7) and (8) respectively and for narrow band downconversion in gures (9) and (10) respectively. the input referred two tone intermodulation test condition spectrum at maximum power setting is shown in gure (11). the typical input nf and gain versus frequency and nf speci cation limits, over selectable power settings are contained in gures (12), (13) and (14) respectively. the output of the preampli er is fed to the mixer section which is optimised for low radiation application. in this stage the rf signal is mixed with the local oscillator frequency, which is generated by the on-board oscillator. the oscillator block uses an external tuneable network and is optimised for low phase noise. the typical oscillator application as an upconverter is shown in gure (15) and the typical phase noise performance in gure (16). the typical oscillator application as a downconverter is shown in gure (17), and the phase noise performance in gure (18). this oscillator block interfaces direct with the internal pll to allow for frequency synthesis of the local oscillator. finally the output of the mixer provides an open collector differential output drive. the device allows for selection of an if in the range 30-1400 mhz so covering standard hiifs between 1 and 1.4 ghz and all conventional tuner output ifs. when used as a broadband upconverter to a hiif the output should be differentially loaded, for example with a differential saw lter, to maximise intermodulation performance. a nominal load in maximum power setting is shown in gure (3), which will typically be terminated with a differential 200 ? load. when used as a narrowband downconverter the output should be differentially loaded with a discrete differential to single ended converter as in gure (4), shown tuned to 44 mhz if. alternatively loading can be direct into a differential input ampli er or sawf, in which case external loads to vcc will be required. an example load for 44 mhz application with a gain of 16 db is contained in gure (5). the nf and gain with recommended load versus power setting are contained in gure (19). the typical if output impedance as upconverter and downconverter are contained in gures (20) and (21) respectively. in all applications care should be taken to achieve symmetric balance to the if outputs to maximise intermodulation performance. the typical key performance data at 5v vcc and 25 deg c ambient are shown in the section headed 'quick reference data'.
SL2101 datasheet 4 pll frequency synthesiser the pll frequency synthesiser section contains all the elements necessary, with the exception of a reference frequency source and loop lter to control the oscillator, so forming a complete pll frequency synthesised source. the device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. the lo signal from the oscillator drives an internal preampli er, which provides gain and reverse isolation from the divider signals. the output of the preampli er interfaces direct with the 15-bit fully programmable divider. the programmable divider is of mn+a architecture, where the dual modulus prescaler is 16/17, the a counter is 4-bits, and the m counter is 11 bits. the output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. this frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. in both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in gure (22). typical applications for the crystal oscillator are contained in gure (23a) and gure (23b). figure (23b) is used when driving a second SL2101 as a downconverter. the output of the phase detector feeds a charge pump and loop ampli er, which when used with an external loop lter and high voltage transistor, integrates the current pulses into the varactor line voltage, used for controlling the oscillator. the programmable divider output fpd divided by two and the reference divider output fcomp can be switched to port p0 by programming the device into test mode. the test modes are described in gure (24). the crystal reference frequency can be switched to bufref output by bit re as described in gure (25) programming the SL2101 is controlled by an i 2 c data bus and is compatible with both standard and fast mode formats. data and clock are fed in on the sda and scl lines respectively as de ned by i 2 c bus format. the device can either accept data (write mode), or send data (read mode). the lsb of the address byte (r/w) sets the device into write mode if it is low, and read mode if it is high. tables 1 and 2 in gure (26) illustrate the format of the data. the device can be programmed to respond to several addresses, which enables the use of more than one device in an i 2 c bus system. figure (26), table 3 shows how the address is selected by applying a voltage to the 'add' input. when the device receives a valid address byte, it pulls the sda line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. when the device is programmed into read mode, the controller accepting the data must pull the sda line low during all status byte acknowledge periods to read another status byte. if the controller fails to pull the sda line low during this period, the device generates an internal stop condition, which inhibits further reading. write mode with reference to gure (26), table 1, bytes 2 and 3 contain frequency information bits 2 14 -2 0 inclusive. byte 4 controls the synthesiser reference divider ratio, see gure (22) and the charge pump setting, see gure (27). byte 5 controls the test modes, see gure (24), the buffered crystal reference output select re, see gure (25), the power setting, see gure (6) and the output port p0. after reception and acknowledgement of a correct address (byte 1), the rst bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without re-addressing the device. this procedure continues until a stop condition is received. the stop condition can be generated after any data byte, if however it occurs during a byte transmission, the previous byte data is retained. to facilitate smooth ne tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a stop condition. .
datasheet SL2101 5 read mode when the device is in read mode, the status byte read from the device takes the form shown in gure (26) table 2. bit 1 (por) is the power-on reset indicator, and this is set to a logic '1' if the vcc supply to the device has dropped below 3v (at 25 ? c), e.g. when the device is initially turned on. the por is reset to '0' when the read sequence is terminated by a stop command. when por is set high this indicates that the programmed information may have been corrupted and the device reset to the power up condition. bit 2 (fl) indicates whether the synthesiser is phase locked, a logic '1' is present if the device is locked, and a logic '0' if the device is unlocked. programmable features synthesiser programmable divider function as described above reference programmable divider function as described above. charge pump current the charge pump current can be programmed by bits c1 & c0 within data byte 4, as de ned in gure (27). power setting the device power and hence signal handling can be programmed by bits i2 - i0 within data byte 5, as de ned in gure (6d). in all power settings the synthesiser remains enabled to facilitate rapid pll lock reacquisition test mode the test modes are de ned by bits t2 - t0 as described in gure (24) general purpose ports, p0 the general purpose port can be programmed by bits p0; logic '1' = on logic '0' = off (high impedance) - this is the default state at device power on buffered crystal reference output, the buffered crystal reference frequency can be switched to the bufref bufref output by bit re as described in gure 25. the bufref output defaults to the on condition at device power up. figure 2 - SL2101 block diagram i 2 c bus interface charge pump reference divider lo lob sda scl add xtal xtalcap bufref port p0 drive pump ifoutput fpd/2 fcomp fpd ref osc osc rf rfb ifoutputb gm control 15 bit programmable divider
SL2101 datasheet 6 figure 3 - nominal output load as upconverter into differential sawf figure 4 - nominal output load as downconverter, 44mhz if figure 5 - output load as downconverter to a differential ampli?r 15 14 10nh 10nh vcc SL2101 output outputb 200 ? 200 ? sawf 33 ? 33 ? output 15 pf 15 pf 10 uh 820 nh 820 nh 10 nf 15 14 SL2101 vcc output 15 14 SL2101 10 nf 10 nf outputb vcc 680 nh 680 nh 100 nf
datasheet SL2101 7 * default setting on sl2100 i2 i1 i0 supply current in ma typ max 0 0 0 90 * 120 001 67 89 010 56 75 011 51 68 1 0 0 82 109 101 59 78 110 48 64 111 43 57 figure 6 - supply current figure 7 - typical rf input impedance as broadband upconverter (maximum power setting) figure 8 - rf input impedance matching network as 50-860mhz upconverter 200 ? 100nf 100nf 47nh 9 10 rfinput rfinputb SL2101 rfin 75 ? ch1 s 11 1 u fs start 50.000 000 mhz stop 860.000 000 mhz 4.7v cor av g 16 smo prm z 0 75 27 jul 2001 08:53:57 1 2 3 4 1_: 547.03 -287.34 11.078 pf 50.000 000 mhz 2_: 77.484 -188.18 320 mhz 3_: 32.473 -102.97 590 mhz 4_: 21.506 -62.176 860 mhz ? ? ? ? ? ? ? ? ?
SL2101 datasheet 8 figure 9 - typical rf input impedance as narrow band downconverter (maximum power setting) figure 10 - rf input impedance matching network as 1.22ghz downconverter 2.7pf 10nf 3.9nh 9 10 rfinput rfinputb SL2101 rfin 200 ? ch1 s 11 1 u fs start 1 000.000 000 mhz stop 1 400.000 000 mhz 4.7v cor av g 16 smo prm z 0 75 27 jul 2001 09:05:31 1 2 3 4 1_: 20.07 -46.965 3.3888 pf 1 000.000 000 mhz 2_: 19.795 -34.527 1.15 ghz 3_: 20.666 -26.233 1.25 ghz 4_: 25.772 -15.155 1.4 ghz ? ? ? ? ? ? ? ?
datasheet SL2101 9 figure 11 - two tone intermodulation test condition spectrum, input referred 48 dbuv 94 dbuv iim3 -46dbc f2-f1 f1-df f2+df f1 f2 df 47 dbuv iim2-47dbc
SL2101 datasheet 10 * measured with 128 channels at +7dbmv. i2 i1 i0 typ nf (db) gain (db) typ cso* (dbc) typ ctb* (dbc) typ ipip2 (db v) typ ipip3 (db v) 0 0 0 6.8 10.1 -65 -65 144 121 0 0 1 6.0 9.1 -60 -54 141 114 0 1 0 5.8 7.6 -56 -42 132 108 0 1 1 6.5 5.4 -49 -35 129 106 1 0 0 8.7 10.4 -63 -60 146 117 1 0 1 6.2 10.0 -64 -56 142 113 1 1 0 5.9 8.3 -58 -42 133 106 1 1 1 6.4 5.8 -50 -34 126 103 figure 14 - upconverter gain, nf and intermodulation with recommended load versus power setting figure 12 - input nf, typical (maximum power setting) figure 13 - conversion gain as upconverter (maximum power setting) 0 1 2 3 4 5 6 7 8 9 10 0 100 200 300 400 500 600 700 800 900 input frequency(in mhz) conversion gain(in db) gain 11 0 1 2 3 4 5 6 7 8 0100 200 300 400 500 600 700 800 900 input frequency (mhz) noise figure (db)
datasheet SL2101 11 figure 15 - upconverter oscillator application figure 16 - oscillator typical phase noise performance at 10khz offset figure 15 - upconverter oscillator application -95 -93 -91 -89 -87 -85 0 100 200 300 400 500 600 700 800 900 input frequency(in mhz) phase noise(in dbc/hz) pn 1 k ? varactor line bb555 2 pf bb555 3x2.75 mm (centre) 3x1.5 mm 3x0.5 mm
SL2101 datasheet 12 i2 i1 i0 typ nf (db) gain (db) typ ipip3 (db v) 0 0 0 10.3 15.6 124 0 0 1 9.3 15.1 119 0 1 0 8.8 14.0 112 0 1 1 8.7 12.1 106 1 0 0 11.6 15.4 121.3 1 0 1 9.0 15.1 119.7 1 1 0 8.3 13.9 112.6 1 1 1 8.0 11.9 106.3 figure 19 - downconverter gain, nf and ip3 with recommended (fig. 4)load versus power setting figure 18 - typical phase noise performance as downconverter at 10khz offset 80 82 84 86 88 90 92 94 96 98 100 1040 1060 1080 1100 1120 1140 1160 1180 1200 2201 lo frequency phase noise (at 10 khz offset) figure 17 - downconverter oscillator application 4.3 nh 1 k ? varactor line 2.5 pf bb555 20 21
datasheet SL2101 13 figure 20 - typical if output impedance as upconverter, single-ended figure 21 - typical if output impedance as downconverter, single-ended ch1 s 11 1 u fs start 1 000.000 000 mhz stop 1 400.000 000 mhz 4.7v cor av g 16 smo prm z 0 50 27 jul 2001 11:24:54 1 2 3 4 1_: 4.3164 -99.426 1.6007 pf 1 000.000 000 mhz 2_: 3.7266 -80.117 1.15 ghz 3_: 4.1328 -70.223 1.25 ghz 4_: 4.7617 -58.166 - 5 8 . 1 6 6 1.4 ghz ? ? ? ? ? ? ? ? ? ch1 s 11 1 u fs start 10.000 000 mhz stop 100.000 000 mhz 4.7v cor avg 16 smo prm z 0 50 27 jul 2001 09:48:39 1 2 3 4 1_: 1.3588 k -1.1071 k 7.1882 pf 20.000 000 mhz 2_: 606.87 -695.97 40 mhz 3_: 305.72 -549.5 70 mhz 4_: 213.55 -449.58 100 mhz ? ? ? ? ? ? ? ? ?
SL2101 datasheet 14 r4 r3 r2 r1 r0 ratio 00000 2 00001 4 00010 8 00011 16 00100 32 00101 64 00110 128 00111 256 01000 illegal state 01001 5 01010 10 01011 20 01100 40 01101 80 01110 160 01111 320 10000 illegal state 10001 6 10010 12 10011 24 10100 48 10101 96 10110 192 10111 384 11000 illegal state 11001 7 11010 14 11011 28 11100 56 11101 112 11110 224 11111 448 figure 22 - reference division ratios
datasheet SL2101 15 *clocks need to be present on crystal and local oscillator to enable charge pump test modes and to toggle status byte bit fl t2 t1 t0 test mode description 0 0 0 normal operation 0 0 1 charge pump sink * status byte fl set to logic '0' 0 1 0 charge pump source * status byte fl set to logic '0' 0 1 1 charge pump disabled * status byte fl set to logic '1' 1 0 0 normal operation and port p0 = fpd/2 1 0 1 charge pump sink * status byte fl set to logic '0' port p0 = fcomp 1 1 0 charge pump source * status byte fl set to logic '0' port p0=f comp 1 1 1 charge pump disabled * status byte fl set to logic '1' port p0 = fcomp figure 24 - test modes re bufref output 0 disabled, high impedance 1 enabled figure 25 - buffered crystal reference output select figure 23(a) - standard application figure 23(b) - application when driving two SL2101 from one crystal xtalcap xtal 47pf 47pf 10pf 4mhz 1 2 820nh 10k xtalcap xtal SL2101 upconverter SL2101 downconverter 1 2 xtalcap xtal 47pf 4mhz 47pf 1 2 figures 23(a) and (b) - crystal oscillator applications
SL2101 datasheet 16 a : acknowledge bit ma1,ma0 : variable address bits (see table 3) 2 14 -2 0 : programmable division ratio control bits i2-i0 : lna/mixer power select (see gure (6)) c1-c0 : charge pump current select (see gure (27)) r4-r0 : reference division ratio select (see gure (22)) t2-t0 : test mode control bits (see gure (24)) re : buffered crystal reference output enable (see gure (25)) p0 : p0 port output state por : power on reset indicator fl : phase lock ag # programmed by connecting a 30 k ? resistor between pin and vcc msb lsb address 11000ma1ma00a byte 1 programmable divider 02 14 2 13 2 12 2 11 2 10 2 9 2 8 a byte 2 programmable divider 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 a byte 3 control data 1 c1c0r4r3r2r1r0 a byte 4 control data t2 t1 t0 i2 i1 i0 re p0 a byte 5 table 1 - write data format (msb is transmitted ?st) msb lsb address 11000ma1ma01a byte 1 status byte porfl000000a byte 2 table 2 - read data format (msb is transmitted ?st) ma1 ma0 address input voltage level 0 0 0-0.1vcc 0 1 open circuit 1 0 0.4vcc - 0.6 vcc # 1 1 0.9 vcc - vcc table 3 - address selection c1 c0 current in a min typ max 0 0 +-98 +-130 +-162 0 1 +-210 +-280 +-350 1 0 +-450 +-600 +-750 1 1 +-975 +-1300 +-1625 figure 27 - charge pump current figure 26
datasheet SL2101 17 electrical characteristics test conditions (unless otherwise stated) t amb = -40 ? to 85 ? c, vee= 0v, vcc=5v+-5% these characteristics are guaranteed by either production test or design. they apply within the speci ed ambient temperature and supply voltage at maximum power setting unless otherwise stated. characteristic pin min typ max units conditions supply current 6,12, 17,19, 22 90 120 ma if outputs will be connected to vcc through the differential load as in gures (3), (4) & (5) see gure (6) for programmable settings input frequency range 9, 10 50 1400 mhz operating condition only output frequency range 14, 15 30 1400 mhz operating condition only composite peak input signal 9, 10 97 db v operating condition only all synthesiser related spurs on if output 14, 15 -60 dbc within channel bandwidth of 8 mhz and with input power of 60 db v upconverter application input frequency range 9, 10 50 860 mhz input impedance 75 ? see gure (7) input return loss 6 db with input matching network as in gure (8) input noise figure 9.5 db tamb=27 ? c,see gure (12), with input matching network as in gure (8) see gure (14) for programmable settings conversion gain 9 db differential voltage gain to 200 ? load on output of sawf as in gure (3), see gure (13) see gure (14) for programmable settings gain variation across operation range -1 +1 db 50-860 mhz gain variation within channel 0.5 db channel bandwidth 8 mhz within operating frequency range through gain -20 db 45-1400 mhz cso -65 dbc measured with 128 channels at 62 db v see gure (14) for programmable settings ctb -68 dbc measured with 128 channels at 62 db v see gure (14) for programmable settings ipip2 2t 141 db v see note (2) see gure (14) for programmable settings ipip3 2t 117 db v see note (2) see gure (14) for programmable settings ipim2 2t -47 dbc see note (2) , see gure (11) ipim3 2t -46 dbc see note (2), see gure (11)
SL2101 datasheet 18 lo operating range 1 2.3 ghz maximum tuning range 0.9 ghz determined by application lo phase noise, ssb application as in gure (15), see gure (16) @ 10 khz offset -86 dbc/hz @ 100 khz offset -106 dbc/hz lo phase noise oor -136 dbc/hz application as in gure (15) if output frequency range 14, 15 1 1.4 ghz if output impedance see gure (20) downconverter application input frequency range 9, 10 1000 1400 mhz input impedance 75 ? see gure (9) input return loss 12 db with input matching network as in gure (10) input noise figure 14 db tamb=27 ? c, with input matching network as in gure (10) see gure (19) for programmable settings conversion gain 12 db differential voltage gain to 50 ? load on output of impedance transformer as in gure (5) see gure (19) for programmable settings gain variation within channel 0.5 db channel bandwidth 8 mhz within operating frequency range through gain -20 db 45-1400 mhz ipip3 2t 117 db v see note (2) ipim3 2t -46 dbc see note (2), see gure (11) lo operating range 1 2.3 ghz maximum tuning range determined by application, see note (4) lo phase noise, ssb application as in gure (17). see gure (18) @ 10 khz offset -92 dbc/hz @ 100 khz offset -112 dbc/hz lo phase noise oor -136 dbc/hz application as in gure (17) if output frequency range 14, 15 100 mhz if output impedance see gure (21) synthesiser sda, scl 3, 4 i 2 c 'fast mode' compliant input high voltage 3 5.5 v input low voltage 0 1.5 v input high current 10 a input voltage = vcc input low current -10 a input voltage = vee characteristic pin min typ max units conditions
datasheet SL2101 19 notes (1) all power levels are referred to 75 ? and 0 dbm = 109 db v (2) any two tones within rf operating range at 94 db v beating within band, with output load as in gure (3) (3) port powers up in high impedance state (4) to maximise phase noise the tuning range should be minimised and q of resonator maximised. the application as in gure (17) has a tuning range of 200 mhz. (5) if the bufref output is not used it should be left open circuit or connected to vccd and disabled by setting re = 0 . leakage current 10 a vcc=vee hysterysis 0.4 v sda output voltage 3 0.4 v isink = 3 ma 0.6 v isink = 6 ma scl clock rate 4 400 khz charge pump output current 28 see gure (27), vpin = 2v charge pump output leakage 28 +-3 +-10 na vpin = 2v charge pump drive output current 27 0.5 ma vpin = 0.7v crystal frequency 1, 2 2 20 mhz see gure 23(a) and (b) for application recommended crystal series resistance 10 200 ? 4 mhz parallel resonant crystal external reference input frequency 2 2 20 mhz sinewave coupled through 10 nf blocking capacitor external reference drive level 2 0.2 0.5 vpp sinewave coupled through 10 nf blocking capacitor phase detector comparison frequency 4 mhz equivalent phase noise at phase detector -148 -152 -158 dbc/hz dbc/hz dbc/hz ssb, within loop bandwidth f comp = 1mhz f comp = 250khz f comp = 62.5khz local oscillator programmable divider division ratio 240 32767 reference division ratio see gure (22) output port 26 see note (3) sink current 2 ma vport = 0.7v leakage current 10 a vport =vcc bufref output 5 ac coupled . note (5) output amplitude 0.35 vpp enabled by bit re=1 and default state on power-up output impedance 250 ? address select 24 see gure (26) table (3) input high current 1 ma vin=vcc input low current -0.5 ma vin=vee characteristic pin min typ max units conditions
SL2101 datasheet 20 absolute maximum ratings all voltages are referred to vee at 0v (pins 7, 8, 11, 13, 16, 18, 23, 25) characteristic pin min max units conditions supply voltage, v cc 6, 12, 17, 19, 22 -0.3 6 v rf input voltage 9, 10 117 dbuv differential, ac coupled inputs all i/o port dc offsets -0.3 vcc+0.3 v sda, scl dc offsets 3, 4 -0.3 6 v vcc = vee to 5.25v storage temperature -55 150 ? c junction temperature 125 ? c power applied package thermal resistance, chip to case 20 ? c/w package thermal resistance, chip to ambient 85 ? c/w power consumption at 5.25v 630 mw maximum power setting esd protection (pins 3-28) 1 kv mil-std 883b method 3015 cat1 esd protection (pins 1,2) 0.75 kv
datasheet SL2101 21 rf rfb 9 10 500 500 v ref lo lob 20 21 rf inputs oscillator inputs if output if output b 15 14 if outputs figure 28 - input and output interface circuits (rf section)
SL2101 datasheet 22 24 27 v ccd scl/sda xtal v ccd 220 drive pump 28 * v ccd 500k 120k 40k add v ccd p0 26 enable/ disable bufref v ccd ack xtalcap 2 1 5 * on sda only 200 a 1ma output port bufref output sda/scl (pins 3 and 4) add input reference oscillator loop amplifier figure 29 - input and output interface circuits (pll section)

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